In the integrated circuit (IC) industry, it has become necessary to integrate dual gate oxide (DGO) thicknesses onto a single integrated circuit device. One motivation for performing dual gate oxide processing is that high performance transistors require thinner gate dielectric regions and operate at lower voltages (e.g. 1.8 volts to 2.5 volts), whereas most conventional external peripherals typically require higher operating voltages such as 3.3 volts to 5.0 volts. When interfacing lower voltage high performance MOS transistors to higher voltage devices, input and output (I/O) buffers of the integrated circuit (IC) are typically designed to contain thicker gate dielectric regions that are compatible with the higher external peripheral device voltages. In addition, current microcontroller units (MCUs) and digital signal processors (DSPs) are integrating several different types of technology onto a single integrated circuit. For example, high speed logic, power logic, static random access memory (SRAM), nonvolatile memory (NVM), embedded dynamic random access memory (DRAM), analog circuitry, and other devices and technologies are now being considered for integration onto the same integrated circuit die. Many of these devices require different gate dielectric processing and different gate dielectric thicknesses.
One method to enable the formation of two different gate oxide thicknesses in two different active areas is illustrated in FIGS. 1-4.
FIG. 1 illustrates a prior art semiconductor structure 10. Semiconductor structure 10 has a substrate 12. Trench isolation regions 14 are formed within select portions of the substrate 12. The trench isolation regions 14 separate many active areas of the substrate 12, two of which are illustrated in FIG. 1. Specifically, FIG. 1 illustrates a first active area 16 that is separated from a second active area 18 by one or more trench isolation regions 14.
FIG. 2 illustrates that at thermal oxidation process is used to form an oxide layer 20a in both the active region 16 and the active area region 18. After layer 20a is formed across the entire wafer in both active areas 16 and 18, a photoresist mask 22 is formed to protect the portion of the layer 20a lying within the active area 18. Since the layer 22 does not overlay the active area 16, any portion of the layer 20a located within the active area 16 is exposed to subsequent processing ambients. An oxide etch ambient is then used to etch the layer 20a from the top surface of the active area 16 while the layer 22 protects the underlying layer 20a from the etch ambient. Therefore, the active area 16 of FIG. 2 illustrates that the layer 20a has been removed from a top surface of the active area 16, whereas the layer 20a remains behind on the active area 18.
FIG. 3 illustrates that an O.sub.2 ash process to remove the photoresist layer 22 from a surface of the structure 10. This O.sub.2 ash process involves ion bombardment, and this ion bombardment will convert the oxide layer 20a within active area 18 to a damaged oxide area 20b. The damaged layer 20b is damaged due to the ion bombardment needed to remove the photoresist layer 22 in a manner similar to the damage caused to exposed layers by low energy ion implantation. Following ash photoresist removal, an RCA substrate cleaning process is used to clean the surface of the active area 16. This RCA cleaning process involves oxide etch chemicals, such as HF, wherein a top surface of the layer 20b will be disadvantageously removed by the HF exposure. This removal of a portion of gate oxide layer 20b alone ensures that disadvantageous wafer-to-wafer gate oxide variations will be present. The oxide etch properties of the RCA clean also create addition problems within the structure 10. For example, the HF strip used in the RCA clean will not etch the layer 20b uniformly, thereby resulting in non-uniform distribution of oxide within the active area 18. This nonuniform distribution across a wafer and wafer-to-wafer adversely affects MOS on-current (Id), threshold voltage (Vt), leakage current, charge-to-break-down (Qbd) and like conventional MOSFET parameters. Generally, the ion bombardment from the O.sub.2 ash and the oxide etch ambient from the RCA surface clean will result in substantial degradation of the quality of the oxide 20b in active area 18.
FIG. 4 illustrates that the entire wafer 10 is exposed to a thermal oxidation ambient to form a thin oxide layer 26 within active area 16. This oxidation slightly thickens the layer 20b in active area 18 to form a thickened oxide layer 20c. Due to the previous oxide bombardment damage and non-uniformity resulting within the layer 20b, the layer 20c is also non-uniform, damaged, and has compromised gate oxide integrity as discussed above. The lack of gate oxide integrity for layer 20c makes it is difficult to control MOS transistor performance in active area 18 both wafer-to-wafer and across a single wafer.
Due to the above concerns, there exists in the integrated circuit (IC) industry, a need for an IC manufacturing process which forms dual gate oxide regions of differing thickness on a same IC wafer without the problems illustrated and discussed with respect to FIGS. 1-4.
In addition to the process of FIGS. 1-4, the industry has used nitrogen ion implantation into substrate regions to create dual gate oxide devices. This process can be illustrated with respect to FIG. 1. In FIG. 1, the active area 16 can be selectively implanted with nitrogen atoms where active area 18 is masked from such an implant. Following this implant, a thermal oxidation is performed whereby the nitrogen incorporated into the active area 16 will retard thermal oxidation in that region 16. The result will be the formation of a thinner gate oxide region within active area 16 and a thicker gate oxide region with an active area 18. However, this process has some disadvantages. First, the scalability of the process to future technology is poor. In addition, the gate oxide integrity of the region 16 is significantly reduced according to experimental data, whereby the charge to breakdown (QBD) is adversely decreased. In addition, the obtainable ratio of thicknesses (e.g., thin gate ox thickness divided by thick gate oxide thickness) is inherently limited by physics to a limited range. This limited range of gate oxide differentials may create some artificial design limitations that may be problematic for certain IC designs.
Therefore, the nitrogen implantation scheme, now being investigated in the integrated circuitry industry is not believed to be entirely optimal for all purposes. Therefore, a need exists in the art to create a dual gate oxide process wherein both the thin and the thick gate oxide regions have improved gate oxide integrity, scalability, and flexibility.